Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition Paperback

James Jeffers

Intel Xeon Phi Processor High Performance Programming, Knights Landing Edition, Second Edition, is a practical guide to code development for Intel's Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques that are essential to programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will increase your program performance on any system, and better prepare you for the Xeon Phi Knights Landing coprocessor. The book starts by providing a brief level setting overview of Intel's Knights Landing including Xeon Phi and Xeon architectures, and then quickly uses simple but informative code examples to explain the unique aspects of the new Knights Landing chipset. It then dives deeper into the meat of the hardware and software architecture that is behind the high performing examples, explaining the tools, development environment, and coding best practices to successfully leverage wide vectors, many cores, many threads, and high bandwidth cache/memory architecture. * Discusses how to leverage parallel programming best practices on Intel Xeon Phi Knights Landing* Explains portable, high-performance computing in a familiar and proven threaded, scalar-vector programming model* Features input from Intel insiders with key insights and under-the-hood tips* Offers new content and new examples demonstrating the KNL architecture* Includes downloadable source code and supplemental material from the book's companion web page

0128091940

English

Elsevier Science & Technology

June 17, 2016

Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel (R) MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years. James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012. Avinash Sodani is the chief architect of the Knights Landing Xeon Phi Processor. He has many years of experience architecting high end processors and previously was one of the architects for the first Core(tm) processor codenamed Nehalem.